PEF 82902 F V1.1

D a ta S he e t , D S 1 , N o v . 20 0 1 T-SMINTI 4 B 3 T Se c o n d G e n . Mo d u l a r I S D N N T (I n t e l l i g e n t ) PE F 82 90 2 V er s io n 1 . 1 Wi re d C om m un ic a t io ns N e v e r s t o p t h i n k i n g . Edition 2001-11-09 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. D a ta S he e t , D S 1 , N o v . 20 0 1 T-SMINTI 4 B 3 T Se c o n d G e n . Mo d u l a r I S D N N T (I n t e l l i g e n t ) PE F 82 90 2 V er s io n 1 . 1 Wi re d C om m un ic a t io ns N e v e r s t o p t h i n k i n g . PEF 82902 Revision History: 2001-11-09 Previous Version: Preliminary Data Sheet 06.01 Page DS 1 Subjects (major changes since last revision) Table 18 Additional C/I-command LTD Figure 41 Chapter 2.4.7.4 Chapter 3.2.3 Chapter 4.3 Chapter 4.9.4 The Framer / Deframer Loopback (DLB) is no more supported Chapter 4.3 Reset value of MASKU is FFh (not 00h) Chapter 4.3 Chapter 4.9.8 Reset value of FW-Version is 3Eh Chapter 4.9.4 Restriction of LOOP.LB1, LB2 and LBBD to Transparent state Chapter 5.2 Input Leakage Current AIN, BIN: max. 30µA Chapter 5.4 Reduced power consumption For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com PEF 82902 Table of Contents Page 1 1.1 1.2 1.3 1.4 1.5 1.6 1.6.1 1.7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Not Supported are ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Specific Pins and Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 2.1 2.1.1 2.1.1.1 2.1.2 2.1.3 2.2 2.3 2.3.1 2.3.2 2.3.2.1 2.3.2.2 2.3.3 2.3.3.1 2.3.3.2 2.3.3.3 2.3.3.4 2.3.3.5 2.3.3.6 2.3.4 2.3.5 2.3.5.1 2.3.5.2 2.3.5.3 2.3.5.4 2.3.5.5 2.3.6 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.4.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microcontroller Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Control Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microcontroller Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM‚-2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM‚-2 Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Data Access (CDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Data Strobe Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM‚-2 Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Handshake Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MONITOR Channel Programming as a Master Device . . . . . . . . . . . MONITOR Channel Programming as a Slave Device . . . . . . . . . . . . Monitor Time-Out Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MONITOR Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C/I Channel Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Examples for D-Channel Access Control . . . . . . . . . . . . TIC Bus Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop/Go Bit Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-Channel Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Machine of the D-Channel Arbiter . . . . . . . . . . . . . . . . . . . . . . Activation/Deactivation of IOM®-2 Interface . . . . . . . . . . . . . . . . . . . . . U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4B3T Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maintenance Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coding from Binary to Ternary Data . . . . . . . . . . . . . . . . . . . . . . . . . . . Decoding from Ternary to Binary Data . . . . . . . . . . . . . . . . . . . . . . . . . Monitoring of Code Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 16 16 16 19 21 23 23 27 27 28 30 40 41 41 45 47 47 48 48 49 51 51 52 53 54 55 57 59 59 63 63 64 65 2001-11-09 PEF 82902 Table of Contents Page 2.4.4.2 2.4.5 2.4.6 2.4.7 2.4.7.1 2.4.7.2 2.4.7.3 2.4.7.4 2.4.7.5 2.4.7.6 2.4.8 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.5.1 2.5.5.2 2.5.5.3 2.5.6 2.5.7 Block Error Counter (RDS Error Counter) . . . . . . . . . . . . . . . . . . . . . Scrambler / Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command/Indication Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Machine for Activation and Deactivation . . . . . . . . . . . . . . . . . . . State Machine Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Awake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NT State Machine (IEC-T / NTC-T Compatible) . . . . . . . . . . . . . . . . Inputs to the U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Outputs of the U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NT-States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-Transceiver Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line Coding, Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S/Q Channels, Multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transfer between IOM‚-2 and S0 . . . . . . . . . . . . . . . . . . . . . . . . . Loopback 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control of S-Transceiver / State Machine . . . . . . . . . . . . . . . . . . . . . . . C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Machine NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Machine LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S-Transceiver Enable / Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Structure S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.2 3.2.1 3.2.2 3.2.2.1 3.2.2.2 3.2.3 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Layer 1 Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Generation of 4B3T Signal Elements . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Complete Activation Initiated by Exchange . . . . . . . . . . . . . . . . . . . . . . 99 Complete Activation Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Complete Activation Initiated by NT . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Complete Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Loop 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Layer 1 Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Analog Loop-Back S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Loopback No.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Complete Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Loopback No.2 - Single Channel Loopbacks . . . . . . . . . . . . . . . . . . 106 Local Loopbacks Featured By the LOOP Register . . . . . . . . . . . . . . . 106 External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Power Supply Blocking Recommendation . . . . . . . . . . . . . . . . . . . . . . 108 U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Oscillator Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Data Sheet 65 66 66 67 67 68 71 72 74 75 77 79 79 81 82 82 82 85 87 91 94 95 2001-11-09 PEF 82902 Table of Contents 4 4.1 4.2 4.3 4.3.1 4.3.2 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.5.7 4.5.8 4.5.9 4.6 4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 4.6.6 4.7 4.7.1 4.7.2 4.7.3 4.7.4 4.7.5 4.7.6 4.7.7 4.7.8 4.7.9 4.7.10 4.7.11 Data Sheet Page Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset of U-Transceiver Functions During Deactivation or with C/I-Code RESET 122 Mode Register Evaluation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed C/I Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODEH - Mode Register IOM-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CIR0 - Command/Indication Receive 0 . . . . . . . . . . . . . . . . . . . . . . . . CIX0 - Command/Indication Transmit 0 . . . . . . . . . . . . . . . . . . . . . . . . CIR1 - Command/Indication Receive 1 . . . . . . . . . . . . . . . . . . . . . . . . CIX1 - Command/Indication Transmit 1 . . . . . . . . . . . . . . . . . . . . . . . . Detailed S-Transceiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S_CONF0 - S-Transceiver Configuration Register 0 . . . . . . . . . . . . . . S_CONF2 - S-Transmitter Configuration Register 2 . . . . . . . . . . . . . . S_STA - S-Transceiver Status Register . . . . . . . . . . . . . . . . . . . . . . . S_CMD - S-Transceiver Command Register . . . . . . . . . . . . . . . . . . . . SQRR - S/Q-Channel Receive Register . . . . . . . . . . . . . . . . . . . . . . . SQXR- S/Q-Channel Transmit Register . . . . . . . . . . . . . . . . . . . . . . . ISTAS - Interrupt Status Register S-Transceiver . . . . . . . . . . . . . . . . . MASKS - Mask S-Transceiver Interrupt . . . . . . . . . . . . . . . . . . . . . . . . S_MODE - S-Transceiver Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt and General Configuration Registers . . . . . . . . . . . . . . . . . . . . ISTA - Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MASK - Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODE1 - Mode1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODE2 - Mode2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID - Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRES - Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed IOM®-2 Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CDAxy - Controller Data Access Register xy . . . . . . . . . . . . . . . . . . . . XXX_TSDPxy - Time Slot and Data Port Selection for CHxy . . . . . . . CDAx_CR - Control Register Controller Data Access CH1x . . . . . . . . S_CR - Control Register S-Transceiver Data . . . . . . . . . . . . . . . . . . . CI_CR - Control Register for CI1 Data . . . . . . . . . . . . . . . . . . . . . . . . MON_CR - Control Register Monitor Data . . . . . . . . . . . . . . . . . . . . . SDS1_CR - Control Register Serial Data Strobe 1 . . . . . . . . . . . . . . . SDS2_CR - Control Register Serial Data Strobe 2 . . . . . . . . . . . . . . . IOM_CR - Control Register IOM Data . . . . . . . . . . . . . . . . . . . . . . . . . MCDA - Monitoring CDA Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STI - Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 114 114 114 116 123 124 124 124 126 126 127 128 128 129 129 130 131 132 133 134 134 135 135 136 137 139 139 140 140 140 141 142 143 144 145 146 147 148 149 149 2001-11-09 PEF 82902 Table of Contents Page 4.7.12 4.7.13 4.8 4.8.1 4.8.2 4.8.3 4.8.4 4.8.5 4.8.6 4.9 4.9.1 4.9.2 4.9.3 4.9.4 4.9.5 4.9.6 4.9.7 4.9.8 ASTI - Acknowledge Synchronous Transfer Interrupt . . . . . . . . . . . . . MSTI - Mask Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . Detailed MONITOR Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . MOR - MONITOR Receive Channel . . . . . . . . . . . . . . . . . . . . . . . . . . MOX - MONITOR Transmit Channel . . . . . . . . . . . . . . . . . . . . . . . . . . MOSR - MONITOR Interrupt Status Register . . . . . . . . . . . . . . . . . . . MOCR - MONITOR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . MSTA - MONITOR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . MCONF - MONITOR Configuration Register . . . . . . . . . . . . . . . . . . . . Detailed U-Transceiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OPMODE - Operation Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . UCIR - C/I Code Read Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UCIW - C/I Code Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LOOP - Loopback Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RDS - Block Error Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . ISTAU - Interrupt Status Register U-Interface . . . . . . . . . . . . . . . . . . . MASKU - Mask Register U-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . FW_VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 151 151 151 152 152 153 154 154 155 155 155 155 156 157 157 158 159 5 5.1 5.2 5.3 5.4 5.5 5.6 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM®-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial µP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel µP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage Detection Characteristics . . . . . . . . . . . . . . . . . . . . . . . 160 160 161 163 163 163 165 166 168 169 173 174 6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 7 7.1 7.1.1 7.1.2 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 Appendix: Differences between Q- and T-SMINT‚I . . . . . . . . . . . . . . . Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Pin ACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-Interface Conformity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . U-Transceiver State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command/Indication Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 178 179 179 179 180 180 181 184 185 187 2001-11-09 PEF 82902 Table of Contents Page 7.3 External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 8 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Data Sheet 2001-11-09 PEF 82902 List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Page Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Application Example T-SMINT®I: High Feature Intelligent NT. . . . . . . 13 Control via µP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Control via IOM‚-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Serial Command Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Direct/Indirect Register Address Mode . . . . . . . . . . . . . . . . . . . . . . . . 22 Reset Generation of the T-SMINT‚I . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 IOM-2 Frame Structure of the T-SMINT‚I . . . . . . . . . . . . . . . . . . . . . 27 Architecture of the IOM‚-2 Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Data Access via CDAx0 and CDAx1 register pairs . . . . . . . . . . . . . . . 31 Examples for Data Access via CDAxy Registers. . . . . . . . . . . . . . . . . 32 Data Access when Looping TSa from DU to DD . . . . . . . . . . . . . . . . . 33 Data Access when Shifting TSa to TSb on DU (DD) . . . . . . . . . . . . . . 34 Example for Monitoring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Interrupt Structure of the Synchronous Data Transfer . . . . . . . . . . . . . 38 Examples for the Synchronous Transfer Interrupt Control with one STIxy enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Data Strobe Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 MONITOR Channel Protocol (IOM®-2) . . . . . . . . . . . . . . . . . . . . . . . . 43 Monitor Channel, Transmission Abort requested by the Receiver. . . . 46 Monitor Channel, Transmission Abort requested by the Transmitter. . 46 Monitor Channel, Normal End of Transmission . . . . . . . . . . . . . . . . . . 46 MONITOR Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 CIC Interrupt Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 D-Channel Arbitration: µC with HDLC and Direct Access to TIC Bus . 51 D-Channel Arbitration: µC with HDLC and no Access to TIC Bus . . . . 52 Structure of Last Octet of Ch2 on DU . . . . . . . . . . . . . . . . . . . . . . . . . 53 Structure of Last Octet of Ch2 on DD . . . . . . . . . . . . . . . . . . . . . . . . . 54 State Machine of the D-Channel Arbiter (Simplified View). . . . . . . . . . 56 Deactivation of the IOM®-2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 State Diagram Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Awake Procedure initiated by the LT . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Awake Procedure initiated by the NT. . . . . . . . . . . . . . . . . . . . . . . . . . 69 NT State Machine (IEC-T/NTC-T Compatible). . . . . . . . . . . . . . . . . . . 71 Interrupt Structure U-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 S/T -Interface Line Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Frame Structure at Reference Points S and T (ITU I.430). . . . . . . . . . 80 S-Transceiver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 State Machine NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Data Sheet 2001-11-09 PEF 82902 List of Figures Page Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 Figure 73 Figure 74 Figure 75 Figure 76 Figure 77 Figure 78 Figure 79 State Machine LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Interrupt Structure S-Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Activation Initiated by Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Activation Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Activation Initiated by NT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Complete Deactivation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Loop 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Test Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 External Loop at the S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Complete Loopback Options in NT-Mode . . . . . . . . . . . . . . . . . . . . . 106 Loopbacks Featured by Register LOOP . . . . . . . . . . . . . . . . . . . . . . 107 Power Supply Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 External Circuitry U-Transceiver with External Hybrid . . . . . . . . . . . . 109 External Circuitry S-Interface Transmitter . . . . . . . . . . . . . . . . . . . . . 112 External Circuitry S-Interface Receiver . . . . . . . . . . . . . . . . . . . . . . . 112 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Address Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 T-SMINT‚I Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . 115 Maximum Sinusoidal Ripple on Supply Voltage . . . . . . . . . . . . . . . 164 Input/Output Waveform for AC Tests. . . . . . . . . . . . . . . . . . . . . . . . . 165 IOM®-2 Interface - Bit Synchronization Timing . . . . . . . . . . . . . . . . . 166 IOM®-2 Interface - Frame Synchronization Timing . . . . . . . . . . . . . . 166 Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Microprocessor Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Multiplexed Address Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Microprocessor Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Reset Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Undervoltage Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 NTC-Q Compatible State Machine Q-SMINT‚I: 2B1Q . . . . . . . . . . . . 181 Simplified State Machine Q-SMINT‚I: 2B1Q . . . . . . . . . . . . . . . . . . . 182 IEC-T/NTC-T Compatible State Machine T-SMINT‚I: 4B3T. . . . . . . . 183 Interrupt Structure U-Transceiver Q-SMINT‚I: 2B1Q . . . . . . . . . . . . . 185 Interrupt Structure U-Transceiver T-SMINT‚I: 4B3T. . . . . . . . . . . . . . 186 External Circuitry Q- and T-SMINT‚I . . . . . . . . . . . . . . . . . . . . . . . . . 190 Data Sheet 2001-11-09 PEF 82902 List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 41 Data Sheet Page NT Products of the 2nd Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ACT States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Interface Selection for the T-SMINT‚I. . . . . . . . . . . . . . . . . . . . . . . . . . 16 Header Byte Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bus Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 MCLK Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Reset Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Examples for Synchronous Transfer Interrupts . . . . . . . . . . . . . . . . . . 37 Transmit Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Receive Direction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 T-SMINT‚I Configuration Settings in Intelligent NT Applications . . . . . 55 Frame Structure A for Downstream Transmission LT to NT . . . . . . . . 61 Frame Structure B for Upstream Transmission NT to LT. . . . . . . . . . . 62 MMS 43 Coding Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4B3T Decoding Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Active States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Differences to the former NT-SM of the IEC-T/NTC-T . . . . . . . . . . . . . 72 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 M Symbol Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Signal Output on Uk0 in State Test . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 C/I-Code Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 S/Q-Bit Position Identification and Multi-Frame Structure . . . . . . . . . . 81 4B3T Signal Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Generation of the 4B3T Signal Elements. . . . . . . . . . . . . . . . . . . . . . . 97 S/T-Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 U-Transformer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 S-Transformer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Crystal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Reset of U-Transceiver Functions During Deactivation or with C/I-Code RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Mode Register with Immediate Evaluation and Execution. . . . . . . . . 123 Maximum Input Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 S-Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 U-Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Reset Input Signal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Parameters of the UVD/POR Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 174 Design Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 ACT States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 2001-11-09 PEF 82902 Overview 1 Overview The PEB 82902 (T-SMINTâI) offers U-transceiver, S-transceiver and an IOMâ-2 interface. A microcontroller interface provides access to both transceivers as well as the IOMâ-2 interface. However, as opposed to its bigger brother T-SMINTâIX, the T-SMINTâI does not have an HDLC controller. Main target applications of the T-SMINTâI are intelligent NT applications where the HDLC controller(s) is (are) provided by the microcontroller. An example for such a microcontroller is the Infineon UTAH chip which features four flexible HDLC controllers. Table 1 on Page 1 summarizes the 2nd generation NT products. • Table 1 NT Products of the 2nd Generation PEF 80902 PEF 81902 PEF 82902 T-SMINT®O T-SMINT®IX T-SMINT®I Package P-MQFP-44 P-MQFP-64 P-TQFP-64 P-MQFP-64 P-TQFP-64 Register access no U+S+HDLC+ IOMâ−2 U+S+IOMâ−2 Access via n.a MCLK, watchdog timer, SDS, BCL, Dchannel arbitration, IOMâ−2 access and manipulation etc. provided no yes yes HDLC controller no yes no NT1 mode available yes (only) no no Data Sheet parallel (or SCI or IOMâ−2) parallel (or SCI or IOMâ−2) 1 2001-11-09 PEF 82902 Overview 1.1 References [1] TS 102 080, Transmission and Multiplexing; ISDN basic rate access; Digital transmission system on metallic local lines, ETSI, November 1998 [2] FTZ 1 TR 220 Technische Richtlinie, Spezifikation der ISDN Schnittstelle Uk0 Schicht 1, Deutsche Telecom AG, August 1991 [3] TS 0284/96 Technische Spezifikation Intelligenter Netzabschluß (iNT) mit den Funktionen eines Terminaladapters TA 2a/b (ohne Internverkehr), Deutsche Telekom AG, März 2001 [4] pr ETS 300 012 Draft, ISDN; Basic User Network Interface (UNI), ETSI, November 1996 [5] T1.605-1991, ISDN-Basic Access Interface for S and T Reference Points (Layer 1 Specification), ANSI, 1991 [6] I.430, ISDN User-Network Interfaces: Layer 1 Recommendations, ITU, November 1988 [7] IEC-T, ISDN Echocancellation Circuit, PEB 20901 (IEC - TD) / PEB 20902 (IEC - TA), preliminary Target Specification 11.88, Siemens AG, 1988 [8] SBCX, S/T Bus Interface Circuit Extended, PEB 2081 V3.4, User’s Manual 11.96, Siemens AG, 1996 [9] NTC-T, Network Termination Controller (4B3T), PEB 8090 V1.1, Data Sheet 06.98, Siemens AG, 1998 [10] INTC-Q, Intelligent Network Termination Controller (2B1Q), PEB 8191 V1.1, Data Sheet 10.97, Siemens AG, 1997 [11] Q-SMINTO, 2B1Q Second Gen. Modular ISDN NT (Ordinary), PEF 80912 Q-SMINTIX, 2B1Q Second Gen. Modular ISDN NT (Intelligent eXended), PEF 81912 Q-SMINTI, 2B1Q Second Gen. Modular ISDN NT (Intelligent), PEF 82912 V1.3, Data Sheets 03.01, Infineon AG, 2001 [12] IOMâ-2 Interface Reference Guide, Siemens AG, 03.91 [13] SCOUT-S(X), Siemens Codec with S/T-Transceiver, PSB 2138x V1.1, Preliminary Data Sheet 08.98, Infineon Technologies AG, 1999 [14] PITA, PCI Interface for Telephony/Data Applications V0.3, SICAN GmbH, September1997 [15] Dual Channel SLICOFI-2, HV-SLIC; DUSLIC; PEB3265, 4265, 4266; Data Sheet DS2, Infineon Technologies, July 2000. • Data Sheet 2 2001-11-09 T-SMINT®I 4B3T Second Gen. Modular ISDN NT (Intelligent) PEF 82902 Version 1.1 • 1.2 CMOS Features Features known from the PEB 8090 • U-transceiver and S-transceiver on one chip • U-interface (4B3T) conform to ETSI [1] and FTZ [2]: – Meets all transmission requirements on all ETSI and FTZ loops with margin • S/T-interface conform to ETSI [4], ANSI [5] and ITU [6] – Supports point-to-point and bus configurations – Meets and exceeds all transmission requirements • Access to IOMâ-2 C/I and Monitor channels • Power-on reset and Undervoltage Detection with no external components • ESD robustness 2kV P-MQFP-64-1,-2 • P-TQFP-64-1 New Features • Conforms to ’Technische Spezifikation Intelligenter Netzabschluß (iNT) mit den Funktionen eines Terminaladapters TA 2a/b’ of Deutsche Telekom AG [3] • Perfectly suited for high-end intelligent NTs that require multiple HDLC controllers • Pin compatible with Q-SMINTâI (2nd Generation) • Parallel or serial µP-interface – Siemens/Intel non-multiplexed (direct or indirect addressing (SCOUT)) – Siemens/Intel multiplexed – Motorola – programmable MCLK (can be disabled) (SCOUT) Type Package PEF 82902 P-MQFP-64 PEF 82902 P-TQFP-64 Data Sheet 3 2001-11-09 PEF 82902 Overview • Enhanced IOMâ−2 interface – Timeslot access and manipulation (SCOUT) – BCL output; programmable and flexible strobes SDS1/2, e.g. active during several timeslots. – Optional: All registers can be read and written to via new Monitor channel concept – External Awake (EAW) • Optional: Implementation of S-transceiver statemachine in software • Power Down and reset states (e.g. S-transceiver) for individual circuits • Automatic D-channel arbitration between S-bus and external HDLC controller • Priority setting (8/10) for off-chip HDLC controller • Pin Vref and the according external capacitor removed • Inputs accept 3.3V and 5V • I/O (open drain) accepts pull-up to 3.3V1) • Lowest power consumption due to – Low power CMOS technology (0.35µ) – Newly optimized low power libraries – High output swing on U- and S-line interface leads to minimized power consumption – Single 3.3 Volt power supply 1.3 Not Supported are ... • No integrated hybrid is provided by the T-SMINTâI. Therefore, an external hybrid is always required, which consists of only two additional resistors as compared to an integrated hybrid, but allows for more flexibility in board design. • On-chip HDLC controller • Auxiliary IOMâ−2 interface • SRA (capacitive receiver coupling is not suited for S-feeding) • NT-Star with star point on the IOM®-2 bus (already not supported in NTC-T). • No access to S2-5 channels. Access only to S1 and Q channel as in Scout-S. No selection betweeen transparent and non-auto mode provided. 1) Pull-ups to 5V must be avoided. A so-called ’hot-electron-effect’ would lead to long term degradation. Data Sheet 4 2001-11-09 PEF 82902 Overview 1.4 Pin Configuration A4 A3 A2 A1 A0 BCL DU DD SR2 SR1 VDDa_SX VSSa_SX SX2 SX1 TP1 • 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 /VDDDET TP2 VDDa_SR VSSa_SR A5 A6 33 49 50 32 51 30 31 52 53 ® T-SMINT I PEF 82902 54 55 56 57 60 61 21 20 19 62 63 18 17 64 2 3 4 5 6 7 VSSa_UR VDDa_UR AIN BIN /RST /RSTO SDS2 Data Sheet 26 24 23 22 58 59 1 Figure 1 28 27 25 8 9 10 11 12 13 14 15 16 SDS1 ALE /WR or R/W /RD or /DS /CS VDDD VSSD /INT XOUT XIN BOUT VDDa_UX VSSa_UX AOUT 29 FSC DCL VSSD VDDD AD7 or SDX AD6 or SDR AD5 or SCLK AD4 AD3 AD2 AD1 AD0 /EAW MCLK /ACT pin_2.vsd Pin Configuration 5 2001-11-09 PEF 82902 Overview 1.5 Block Diagram • XIN SR1 XOUT VDDDET Clock Generation SR2 RST RSTO POR/UVD AOUT BOUT SX1 S-Transceiver SX2 U-Tansceiver AIN D-Channel Arbitration TP1 BIN M O N Factory Tests TP2 C/I TIC C D A W D T LED µP Interface (e.g. Multiplexed Mode) IOM-2 Interface FSC DCL BCL DU DD SDS1 SDS2 ACT AD0-AD7 ALE RD WR CS INT MCLK EAW block diagram.vsd Figure 2 Data Sheet Block Diagram 6 2001-11-09 PEF 82902 Overview 1.6 Pin Definitions and Functions • Table 2 Pin Definitions and Functions Pin Symbol Type Function 2 VDDa_UR – Supply voltage for U-Receiver (3.3 V ± 5 %) 1 VSSa_UR – Analog ground (0 V) U-Receiver 62 VDDa_UX – Supply voltage for U-Transmitter (3.3 V ± 5 %) 63 VSSa_UX – Analog ground (0 V) U-Transmitter 51 VDDa_SR – Supply voltage for S-Receiver (3.3 V ± 5 %) 52 VSSa_SR – Analog ground (0 V) S-Receiver 46 VDDa_SX – Supply voltage for S-Transmitter (3.3 V ± 5 %) 45 VSSa_SX – Analog ground (0 V) S-Transmitter 29 VDDD – Supply voltage digital circuits (3.3 V ± 5 %) 30 VSSD – Ground (0 V) digital circuits 13 VDDD – Supply voltage digital circuits (3.3 V ± 5 %) 14 VSSD – Ground (0 V) digital circuits 32 FSC O Frame Sync: 8-kHz frame synchronization signal 31 DCL O Data Clock: IOMâ-2 interface clock signal (double clock): 1.536 MHz 35 BCL O Bit Clock: The bit clock is identical to the IOMâ-2 data rate (768 kHz) 33 DD I/O OD Data Downstream: Data on the IOMâ-2 interface 34 DU I/O OD Data Upstream: Data on the IOMâ-2 interface Data Sheet 7 2001-11-09 PEF 82902 Overview Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Type Function 8 SDS1 O Serial Data Strobe1: Programmable strobe signal for time slot and/or D-channel indication on IOMâ-2 7 SDS2 O Serial Data Strobe2: Programmable strobe signal for time slot and/or D-channel indication on IOMâ-2 12 CS I Chip Select: A low level indicates a microcontroller access to the T-SMINTâI 26 SCLK I 26 AD5 I/O Serial Clock: Clock signal of the SCI interface if a serial interface is selected Multiplexed Bus Mode: Address/data bus Address/data line AD5 if the parallel interface is selected Non-Multiplexed Bus Mode: Data bus Data line D5 if the parallel interface is selected 27 SDR I 27 AD6 I/O Data Sheet Serial Data Receive: Receive data line of the SCI interface if a serial interface is selected Multiplexed Bus Mode: Address/data bus Address/data line AD6 if the parallel interface is selected Non-Multiplexed Bus Mode: Data bus Data line D6 if the parallel interface is selected 8 2001-11-09 PEF 82902 Overview Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Type Function 28 SDX OD/O 28 AD7 I/O Serial Data Transmit: Transmit data line of the SCI interface if a serial interface is selected Multiplexed Bus Mode: Address/data bus Address/data line AD7 if the parallel interface is selected Non-Multiplexed Bus Mode: Data bus Data line D7 if the parallel interface is selected 21 22 23 24 25 AD0 AD1 AD2 AD3 AD4 I/O I/O I/O I/O I/O Multiplexed Bus Mode: Address/data bus Transfers addresses from the microcontroller to the T-SMINTâI and data between the microcontroller and the T-SMINTâI. Non-Multiplexed Bus Mode: Data bus. Transfers data between the microcontroller and the T-SMINTâI (data lines D0-D4). 36 37 38 39 40 53 54 A0 A1 A2 A3 A4 A5 A6 I I I I I I I Non-Multiplexed Bus Mode: Address bus transfers addresses from the microcontroller to the T-SMINTâI. For indirect address mode only A0 is valid. Multiplexed Bus Mode Not used in multiplexed bus mode. In this case A0-A6 should directly be connected to VDD. 11 RD I DS I Read Indicates a read access to the registers (Intel bus mode). Data Strobe The rising edge marks the end of a valid read or write operation (Motorola bus mode). Data Sheet 9 2001-11-09 PEF 82902 Overview Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Type Function 10 WR I R/W I Write Indicates a write access to the registers (Intel bus mode). Read/Write A HIGH identifies a valid host access as a read operation and a LOW identifies a valid host access as a write operation (Motorola bus mode). 9 ALE I Address Latch Enable An address on the external address/data bus (multiplexed bus type only) is latched with the falling edge of ALE. ALE also selects the microcontroller interface type (multiplexed or non multiplexed). 5 RST I Reset: Low active reset input. Schmitt-Trigger input with hysteresis of typical 360mV. Tie to ’1’ if not used. 6 RSTO OD Reset Output: Low active reset output. 15 INT OD Interrupt Request: INT becomes active if the T-SMINTâI requests an interrupt. 18 MCLK O Microcontroller Clock: Clock output for the microcontroller 20 EAW I External Awake: A low level on EAW during power down activates the clock generation of the TSMINTâI, i.e. the IOMâ-2 interface provides FSC, DCL and BCL for read and write access.1) 43 SX1 O S-Bus Transmitter Output (positive) 44 SX2 O S-Bus Transmitter Output (negative) 47 SR1 I S-Bus Receiver Input Data Sheet 10 2001-11-09 PEF 82902 Overview Table 2 Pin Definitions and Functions (cont’d) Pin Symbol Type Function 48 SR2 I S-Bus Receiver Input 60 XIN I Crystal 1: Connected to a 15.36 MHz crystal 59 XOUT O Crystal 2: Connected to a 15.36 MHz crystal 64 AOUT O Differential U-interface Output 61 BOUT O Differential U-interface Output 3 AIN I Differential U-interface Input 4 BIN I Differential U-interface Input 49 VDDDET I VDD Detection: This pin selects if the VDD detection is active (’0’) and reset pulses are generated on pin RSTO or whether it is deactivated (’1’) and an external reset has to be applied on pin RST. 17 ACT O Activation LED. Indicates the activation status of U- and Stransceiver. Can directly drive a LED (4mA). 42 TP1 I Test Pin 1. Used for factory device test. Tie to ’VSS’ 50 TP2 I Test Pin 2. Used for factory device test. Tie to ’VSS’ 16, 19, 41, 55 56, 57, 58 1) Tie to ‘1‘ res Reserved These pins are reserved for future use. Do not connect. This function of pin EAW is different to that defined in Ref. [13] Data Sheet 11 2001-11-09 PEF 82902 Overview I: Input O: Output (Push-Pull) OD: Output (Open Drain) 1.6.1 Specific Pins and Test Modes LED Pin ACT A LED can be connected to pin ACT to display four different states (off, slow flashing, fast flashing, on). It displays the activation status of the U- and S-transceiver according to Table 3. or it is programmable via two bits (LED1 and LED2 in register MODE2). Table 3 ACT States Pin ACT LED U_Deactivated U_Activated S_Activated VDD OFF 1 x x 0 0 x 1Hz (3 : 1)* slow flashing 0 1 0 GND 1 1 2Hz (1 : 1)* fast flashing ON 0 Note: * denotes the duty cycle ’high’ : ’low’. with: U_Deactivated: ’Deactivated State’ as defined in Chapter 2.4.7.6. U_Activated: ’SBC Synchronizing’, ’Wait for Info U4H’, and ‘Transparent‘ as defined in Chapter 2.4.7.6. S-Activated: ’Activated State’ as defined in Chapter 2.5.5.2. Note: Optionally, pin ACT can drive a second LED with inverse polarity (connect this additional LED to 3.3V only). Test Modes The test patterns on the S-interface (‘2 kHz Single Pulses‘, ‘96 kHz Continuous Pulses‘) and on the U-interface (‘Data Through‘, ‘Send Single Pulses‘,) are invoked via C/I codes (TM1, TM2, DT, SSP). Setting SRES.RES_U to ‘1‘ forces the U-transceiver into test mode ‘Quiet Mode‘ (QM), i.e. the U-transceiver is hardware reset. Data Sheet 12 2001-11-09 PEF 82902 Overview 1.7 System Integration • DC/DC Converter IDCC PEB2023 S/T - Interface S U - Interface T-SMINTI PEF82902 U POTS Interface µP HV - SLIC SLICOFI - 2 HV - SLIC C 165 Core UTAH 4x HDLC IOM-2 IOM-2 USB/ V.24 USB / V.24 Interface HENTappl.vsd Figure 3 Application Example T-SMINT®I: High Feature Intelligent NT The U-transceiver, the S-transceiver and the IOMâ-2 channels can be controlled and monitored via: a) the parallel or serial microprocessor interface - Access of on-chip registers via µP interface Address/Data format - Activation/Deactivation control of U- and S-transceiver via µP interface and C/I handler - T-SMINTâI is Monitor channel master - TIC bus is transparent on IOMâ−2 interface and is used for D-channel arbitration between S-transceiver and off-chip HDLC controllers. Data Sheet 13 2001-11-09 PEF 82902 Overview • S C/I0 U C/I1 Mon MON IOM -2 C/I Register µc - Interface IOM-2 Slave e.g. SLICOFI-2 µc iommaster.vsd Figure 4 Control via µP Interface Alternatively, the T-SMINTâI can be controlled via b) the IOMâ-2 Interface - Access of on-chip registers via the Monitor channel with Header/Address/Data format (Device is Monitor slave) - Activation/Deactivation control of U- and S-transceiver via the C/I channels CI0 and CI1 - TIC bus is transparent on IOMâ−2 interface and is used for D-channel arbitration between S-transceiver and off-chip HDLC controllers. Data Sheet 14 2001-11-09 PEF 82902 Overview • S C/I1 C/I0 MON U Register IOM -2 INT IOM-2 Master e.g. UTAH iomslave.vsd Figure 5 Data Sheet Control via IOMâ-2 Interface 15 2001-11-09 PEF 82902 Functional Description 2 Functional Description 2.1 Microcontroller Interfaces The T-SMINTâI supports either a serial or a parallel microcontroller interface. For applications where no controller is connected to the T-SMINTâI microcontroller interface, register programming is done via the IOMâ-2 MONITOR channel from a master device. In such applications the T-SMINTâI operates in the IOMâ-2 slave mode (refer to the corresponding chapter of the IOMâ-2 MONITOR handler). The interface selections are all done by pinstrapping. The possible interface selections are listed in Table 4. The selection pins are evaluated when the reset input RST is released. For the pin levels stated in the tables the following is defined: ’High’:dynamic pin value which must be ’High’ when the pin level is evaluated VDD, VSS:static ’High’ or ’Low’ level (tied to VDD, VSS) • Interface Selection for the T-SMINTâI Table 4 PINS WR (R/W) RD (DS) ’High’ ’High’ VSS VSS Serial /Parallel Interface Parallel Serial PINS ALE Interface Type/Mode VDD Motorola VSS Siemens/Intel Non-Mux edge Siemens/Intel Mux ’High’ VSS Serial Control Interface(SCI) VSS VSS IOMâ-2 MONITOR Channel (Slave Mode) CS ‘High’ Note: For a selected interface mode which does not require all pins (e.g. address pins) the unused pins must be tied to VDD. The microcontroller interface also consists of a microcontroller clock generation at pin MCLK, an interrupt request at pin INT, a reset input pin RST and a reset output pin RSTO. The interrupt request pin INT (open drain output) becomes active if the T-SMINTâI requests an interrupt. 2.1.1 Serial Control Interface (SCI) The serial control interface (SCI) is compatible to the SPI interface of Motorola and to the Siemens C510 family of microcontrollers. The SCI consists of 4 lines: SCLK, SDX, SDR and CS. Data is transferred via the lines SDR and SDX at the rate given by SCLK. The falling edge of CS indicates the beginning Data Sheet 16 2001-11-09 PEF 82902 Functional Description of a serial access to the registers. The T-SMINTâI latches incoming data at the rising edge of SCLK and shifts out at the falling edge of SCLK. Each access must be terminated by a rising edge of CS. Data is transferred in groups of 8 bits with the MSB first. Pad mode of SDX can be selected ’open drain’ or ’push-pull’ by programming MODE2.PPSDX. Figure 6 shows the timing of a one byte read/write access via the serial control interface. Data Sheet 17 2001-11-09 PEF 82902 Functional Description • Write Access CS SCLK Header SDR Command/Address Data 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 `0` write SDX Read Access CS SCLK Header SDR Command/Address 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 `1` read Data SDX 7 6 5 4 3 2 1 0 SCI_TIM.VSD Figure 6 Data Sheet Serial Control Interface Timing 18 2001-11-09 PEF 82902 Functional Description 2.1.1.1 Programming Sequences The basic structure of a read/write access to the T-SMINTâI registers via the serial control interface is shown in Figure 7. • write sequence: write byte 2 0 header SDR 7 address (command) 0 7 6 read sequence: byte 3 write data 0 7 0 read byte 2 header SDR 1 7 address (command) 0 7 6 0 7 SDX Figure 7 byte 3 0 read data Serial Command Structure A new programming sequence starts with the transfer of a header byte. The header byte specifies different programming sequences allowing a flexible and optimized access to the individual functional blocks of the T-SMINTâI. The possible sequences are listed in Table 5 and are described after that. • Table 5 Header Byte 40H Header Byte Code Sequence Adr-Data-Adr-Data 48H 43H Sequence Type non-interleaved Access to Address Range 00H-7FH interleaved Adr-Data-Data-Data Read-/Write-only 41H non-interleaved 49H interleaved Address Range 00H-7FH Header 40H: Non-interleaved A-D-A-D Sequences The non-interleaved A-D-A-D sequences give direct read/write access to the address range 00H-7FH and can have any length. In this mode SDX and SDR can be connected Data Sheet 19 2001-11-09 PEF 82902 Functional Description together allowing data transmission on one line. Example for a read/write access with header 40H: SDR header wradr wrdata rdadr SDX rdadr rddata wradr wrdata rddata Header 48H: Interleaved A-D-A-D Sequences The interleaved A-D-A-D sequences give direct read/write access to the address range 00H-7FH and can have any length. This mode allows a time optimized access to the registers by interleaving the data on SDX and SDR. Example for a read/write access with header 48H: SDR header wradr wrdata rdadr SDX rdadr wradr rddata rddata wrdata Header 43H: Read-/Write- only A-D-D-D Sequence Generally, it can be used for any register access to the address range 20H-7DH. The sequence can have any length and is terminated by the rising edge of CS. Example for a write access with header 43H: SDR header wradr wrdata wrdata wrdata wrdata wrdata wrdata wrdata (wradr) (wradr) (wradr) (wradr) (wradr) (wradr) (wradr) SDX Example for a read access with header 43H: SDR header SDX rdadr rddata rddata rddata rddata rddata rddata rddata (rdadr) (rdadr) (rdadr) (rdadr) (rdadr) (rdadr) (rdadr) Header 41H: Non-interleaved A-D-D-D Sequence This sequence (header 41H) allows in front of the A-D-D-D write access a noninterleaved A-D-A-D read access. Generally, it can be used for any register access to the address range 20H-7DH.The termination condition of the read access is the reception of the wradr. The sequence can have any length and is terminated by the rising edge of CS. Data Sheet 20 2001-11-09 PEF 82902 Functional Description Example for a read/write access with header 41H: SDR header rdadr SDX rdadr rddata wradr wrdata wrdata wrdata (wradr) (wradr) (wradr) rddata Header 49H: Interleaved A-D-D-D Sequence This sequence (header 49H) allows in front of the A-D-D-D write access an interleaved A-D-A-D read access. Generally, it can be used for any register access to the address range 20H-7DH.The termination condition of the read access is the reception of the wradr. The sequence can have any length and is terminated by the rising edge of CS. Example for a read/write access with header 49H: SDR header SDX rdadr rdadr rddata 2.1.2 wradr wrdata wrdata wrdata (wradr) (wradr) (wradr) rddata Parallel Microcontroller Interface The 8-bit parallel microcontroller interface with address decoding on chip allows an easy and fast microcontroller access. The parallel interface of the T-SMINTâI provides three types of µP busses which are selected via pin ALE. The bus operation modes with corresponding control pins are listed in Table 6. • Table 6 Bus Operation Modes Bus Mode Pin ALE Control Pins (1) Motorola VDD CS, R/W, DS (2) Siemens/Intel non-multiplexed VSS CS, WR, RD (3) Siemens/Intel multiplexed Edge CS, WR, RD, ALE The occurrence of an edge on ALE, either positive or negative, at any time during the operation immediately selects the interface type (3). A return to one of the other interface types is possible only if a hardware reset is issued. Note: For a selected interface mode which does not require all pins (e.g. address pins) the unused pins must be tied to VDD. A read/write access to the T-SMINTâI registers can be done in multiplexed or nonmultiplexed mode. In non-multiplexed mode the register address must be applied to the address bus (A0A6) for the data access via the data bus (D0-D7). Data Sheet 21 2001-11-09 PEF 82902 Functional Description In multiplexed mode the address on the address bus (AD0-AD7) is latched in by ALE before a read/write access via the address/data bus is performed. The T-SMINTâI provides two different ways to address the register contents which can be selected with the AMOD bit in the MODE2 register. The address mode after reset is the indirect address mode (AMOD = ’0’). Reprogramming into the direct address mode (AMOD = ’1’) has to take place in the indirect address mode. Figure 8 illustrates both register addressing modes. Direct address mode (AMOD = ’1’): The register address to be read or written is directly set in the way described above. Indirect address mode (AMOD = ’0’): • non-muxed: only the LSB of the address bus (A0) • muxed: only the LSB of the address-data bus (AD0) gets evaluated to address a virtual ADDRESS (0H) and a virtual DATA (1H) register. Every access to a target register consists of: • a write access (muxed or non-muxed) to ADDRESS to store the target register´s address, as well as • a read access (muxed or non-muxed) from DATA to read from the target register or • a write access (muxed or non-muxed) to DATA to write to the target register • Direct Address Mode AMOD = ´1´ Indirect Address Mode AMOD = ´0´ (default) D7 - D0 A6 - A0 D7 - D0 Data A0 Data 7Fh 7Eh 7Dh 7Ch 04h 03h 02h 01h 1h DATA 00h 0h ADDRESS regacces.vsd Figure 8 Data Sheet Direct/Indirect Register Address Mode 22 2001-11-09 PEF 82902 Functional Description 2.1.3 Microcontroller Clock Generation The microcontroller clock is derived from the unregulated 15.36 MHz clock from the oscillator and provided by the pin MCLK. Five clock rates are selectable by a programmable prescaler which is controlled by the bits MODE1.MCLK and MODE1.CDS corresponding to the following table. Table 7 MCLK Frequencies MODE1. MCLK Bits MCLK frequency with MODE1.CDS = ’0’ MCLK frequency with MODE1.CDS = ’1’ 0 0 3.84 MHz 7.68 MHz 0 1 0.96 MHz 1.92 MHz 1 0 7.68 MHz 15.36 MHz 1 1 disabled disabled The clock rate is changed after CS becomes inactive. 2.2 Reset Generation Figure 9 shows the organization of the reset generation of the T-SMINTâI. Data Sheet 23 2001-11-09 PEF 82902 Functional Description •. RSS1 125µs ≤ t ≤ 250µs C/I0 Code Change (Exchange Awake) ´0´ RSTO ´1,x´ ´1´ ≥1 ´0,0´ RSS2,1 t = 125µs Watchdog ´0,1´= open RSS2,1 Deactivation Delay Reset MODE1 Register Software Reset Register (SRES) ´1´ ´0´ VDDDET RES_CI Reset Functional Block POR/UVD RES_HDLC RES_S ´0´ ´1´ RES_U VDDDET ≥1 Internal Reset of all Registers RST Pin RESETGEN.VSD Figure 9 Reset Generation of the T-SMINTâI1) Reset Source Selection The internal reset sources C/I code change and Watchdog timer can be output at the low active reset pin RSTO. These reset sources can be selected with the RSS2,1 bits in the MODE1 register according to Table 8. 1) The ’OR’-gates shall illustrate in a symbolic way, that ’source A active’ or ’source B active’ is forwarded. The real polarity of the different sources is not considered. Data Sheet 24 2001-11-09 PEF 82902 Functional Description The internal reset sources set the MODE1 register to its reset value. Table 8 1) Reset Source Selection RSS2 Bit 1 RSS1 Bit 0 C/I Code Change Watchdog Timer POR/UVD1) and RST 0 0 -- -- x 0 1 1 0 x -- x 1 1 -- x x /RSTO disabled (= high impedance) POR/UVD can be enabled/disabled via pin VDDDET • • C/I Code Change (Exchange Awake) A change in the downstream C/I channel (C/I0) generates a reset pulse of 125 µs ≤ t ≤ 250 µs. • Watchdog Timer After the selection of the watchdog timer (RSS = ’11’) an internal timer is reset and started. During every time period of 128 ms the microcontroller has to program the WTC1- and WTC2 bits in the following sequence to reset and restart the watchdog timer: 1. 2. WTC1 WTC2 1 0 0 1 Otherwise the timer expires and a WOV-interrupt (ISTA Register) together with a reset out pulse on pin RSTO of 125 µs is generated. Deactivation of the watchdog timer is only possible with a hardware reset (including expiration of the watchdog timer). As in the SCOUT-S, the watchdog timer is clocked with the IOMâ-2 clocks and works only if the internal IOMâ-2 clocks are active. Hence, the power consumption is minimized in state power down. Software Reset Register (SRES) Several main functional blocks of the T-SMINTâI can be reset separately by software setting the corresponding bit in the SRES register. This is equivalent to a hardware reset of the corresponding functional block. The reset state is activated as long as the bit is set to ’1’. Data Sheet 25 2001-11-09 PEF 82902 Functional Description External Reset Input At the RST input an external reset can be applied forcing the T-SMINTâI in the reset state. This external reset signal is additionally fed to the RSTO output. After release of an external reset, the µC has to wait for min. tµC before it starts read or write access to the T-SMINTâI (see Table 37). Reset Ouput If VDDDET is active, then the deactivation of a reset output on RSTO is delayed by tDEACT (see Table 38). Reset Generation The T-SMINTâI has an on-chip reset generator based on a Power-On Reset (POR) and Under Voltage Detection (UVD) circuit (see Table 38). The POR/UVD requires no external components. The POR/UVD circuit can be disabled via pin VDDDET. The requirements on VDD ramp-up during power-on reset are described in Chapter 5.6.5. Clocks and Data Lines During Reset During reset the data clock (DCL), the bit clock (BCL), the microcontroller clock1) (MCLK) and the frame synchronization (FSC) keep running. During reset DD and DU are high; with the exception of: • The output C/I code from the U-Transceiver on DD IOMâ-2 channel 0 is ’DR’ = 0000 (Value after reset of register UCIR = ’00H’) • The output C/I code from the S-Transceiver on DU IOMâ-2 channel 1 is ’TIM’ = 0000. 1) during a Power-On/UVD Reset, the microcontroller clock MCLK is not running, but starts running as soon as timer tDEAC is started. Data Sheet 26 2001-11-09 PEF 82902 Functional Description 2.3 IOM-2 Interface The T-SMINTâI supports the IOMâ-2 interface in terminal mode (DCL=1.536 MHz) according to the IOMâ-2 Reference Guide [12]. 2.3.1 IOMâ-2 Functional Description The IOMâ-2 interface consists of four lines: FSC, DCL, DD, DU and optionally BCL. The rising edge of FSC indicates the start of an IOMâ-2 frame. The DCL and the BCL clock signals synchronize the data transfer on both data lines DU and DD. The DCL is twice the bit rate, the BCL rate is equal to the bit rate. The bits are shifted out with the rising edge of the first DCL clock cycle and sampled at the falling edge of the second clock cycle. With BCL the bits are shifted out with the rising edge and sampled with the falling edge of the single clock cycle. The IOMâ-2 interface can be enabled/disabled with the DIS_IOM bit in the IOM_CR registerThe FSC signal is an 8 kHz frame sync signal. The number of PCM timeslots on the receive and transmit lines is determined by the frequency of the DCL clock (or BCL), with the 1.536 MHz (BCL=768 kHz) clock 3 channels consisting of 4 timeslots each are available. IOM®-2 Frame Structure of the T-SMINTâI The frame structure on the IOMâ-2 data ports (DU,DD) of the T-SMINTâI with a DCL clock of 1.536 MHz (or BCL=768 kHz) and if TIC bus is not disabled (IOM_CR.TIC_DIS) is shown in Figure 10. • macro_19 Figure 10 Data Sheet IOM-2 Frame Structure of the T-SMINTâI 27 2001-11-09 PEF 82902 Functional Description The frame is composed of three channels: • Channel 0 contains 144-kbit/s of user and signaling data (2B + D), a MONITOR programming channel (MON0) and a command/indication channel (CI0) for control and programming of e.g. the U-transceiver. • Channel 1 contains two 64-kbit/s intercommunication channels (IC), a MONITOR programming channel (MON1) and a command/indication channel (CI1) for control and programming of e.g. the S-transceiver. • Channel 2 is used for D-channel access mechanism (TlC-bus, S/G bit). Additionally, channel 2 supports further IC and MON channels. 2.3.2 IOMâ-2 Handler The IOMâ-2 handler offers a great flexibility for handling the data transfer between the different functional units of the T-SMINTâI and voice/data devices connected to the IOMâ-2 interface. Additionally it provides a microcontroller access to all time slots of the IOMâ-2 interface via the four controller data access registers (CDA). The PCM data of the functional units • S-transceiver (S) and the • Controller data access (CDA) can be configured by programming the time slot and data port selection registers (TSDP). With the TSS bits (Time Slot Selection) the PCM data of the functional units can be assigned to each of the 12 PCM time slots of the IOMâ-2 frame. With the DPS bit (Data Port Selection) the output of each functional unit is assigned to DU or DD respectively. The input is assigned vice versa. With the control registers (CR) the access to the data of the functional units can be controlled by setting the corresponding control bits (EN, SWAP). The IOMâ-2 handler also provides access to the • • • • U and S transceiver MONITOR channel C/I channels (CI0,CI1) TIC bus (TIC) The access to these channels is controlled by the registers S_CR, CI_CR and MON_CR. The IOMâ-2 interface with the two Serial Data Strobes (SDS1,2) is controlled by the control registers IOM_CR, SDS1_CR and SDS2_CR. The following Figure 11 shows the architecture of the IOMâ-2 handler. Data Sheet 28 2001-11-09 PEF 82902 Functional Description • IOM-2 Handler Control Data Access Controller Data Access (CDA) CDA Registers CDA10 CDA11 CDA20 CDA21 (TSDP, DPS, EN, SWAP, TBM, MCDA, STI) CDA_TSDPxy CDA_CRx MCDA STI MSTI ASTI SDS1/2_CR IOM_CR DU MON_CR Control Monitor Data Monitor Data MON Handler DD IOM-2 Interface (EN, OD) TIC Bus Disable DCL BCL/SCLK C/I0 Data C/I0 Data Control C/I1 Data C/I1 CI_CR (EN, TLEN, TSS) SDS1 Microcontroller Interface IOM_CR TIC SDS2 C/I1 Data FSC TIC Bus Data Control Transceiver Data Access (TSS, DPS, EN) D/B1/B2 Data C/I0 Data S_TSDP_B1 S_TSDP_B2 S_CR Transceiver Data (TR=U/S) TR_B1_X TR_B2_X TR_D_X TR_B1_R TR_B2_R TR_D_R TR represents the U and S transceiver 21150_0 7 2001-11-09 29 Data Sheet Architecture of the IOMâ-2 Handler Figure 11 CDA Data PEF 82902 Functional Description 2.3.2.1 Controller Data Access (CDA) The four controller data access registers (CDA10, CDA11, CDA20, CDA21) provide microcontroller access to the 12 IOMâ-2 time slots and more: • looping of up to four independent PCM channels from DU to DD or vice versa over the four CDA registers • shifting or switching of two independent PCM channels to another two independent PCM channels on both data ports (DU, DD). Between reading and writing the data can be manipulated (processed with an algorithm) by the microcontroller. If this is not the case a switching function is performed. • monitoring of up to four time slots on the IOMâ-2 interface simultaneously • microcontroller read and write access to each PCM channel The access principle, which is identical for the two channel register pairs CDA10/11 and CDA20/21, is illustrated in Figure 12. The index variables x,y used in the following description can be 1 or 2 for x, and 0 or 1 for y. The prefix ’CDA_’ from the register names has been omitted for simplification. To each of the four CDAxy data registers a TSDPxy register is assigned by which the time slot and the data port can be determined. With the TSS (Time Slot Selection) bits a time slot from 0...11 can be selected. With the DPS (Data Port Selection) bit the output of the CDAxy register can be assigned to DU or DD respectively. The time slot and data port for the output of CDAxy is always defined by its own TSDPxy register. The input of CDAxy depends on the SWAP bit in the control registers CRx. If the SWAP bit = ’0’ (swap is disabled) the time slot and data port for the input and output of the CDAxy register is defined by its own TSDPxy register. If the SWAP bit = ’1’ (swap is enabled) the input port and time slot of the CDAx0 is defined by the TSDP register of CDAx1 and the input port and time slot of CDAx1 is defined by the TSDP register of CDAx0. The input definition for time slot and data port CDAx0 are thus swapped to CDAx1 and for CDAx1 swapped to CDAx0. The output timeslots are not affected by SWAP. The input and output of every CDAxy register can be enabled or disabled by setting the corresponding EN (-able) bit in the control register CDAx_CR. If the input of a register is disabled the output value in the register is retained. Usually one input and one output of a functional unit (transceiver, CDA register) is programmed to a timeslot on IOMâ-2 (e.g. for B-channel transmission in upstream direction the S-transceiver writes data onto IOMâ-2 and the U-transceiver reads data from IOMâ-2). For monitoring data in such cases a CDA register is programmed as described below under “Monitoring Data”. Besides that none of the IOMâ-2 timeslots must be assigned more than one input and output of any functional unit. Data Sheet 30 2001-11-09 PEF 82902 Functional Description •. TSa TSb DU Control Register CDA_CRx 1 output (EN_O1) input (EN_I1) 1 CDAx1 CDAx0 1 1 1 1 1 0 CDA_TSDPx1 Input Swap (SWAP) input (EN_I0) 0 Time Slot Selection (TSS) Enable Enable 1 1 Data Port Selection (DPS) Time Slot Selection (TSS) 0 0 output (EN_O0) Data Port Selection (DPS) CDA_TSDPx0 1 DD TSa TSb x = 1 or 2; a,b = 0...11 Figure 12 IOM_HAND.FM4 Data Access via CDAx0 and CDAx1 register pairs Looping and Shifting Data Figure 13 gives examples for typical configurations with the above explained control and configuration possibilities with the bits TSS, DPS, EN and SWAP in the registers TSDPxy or CDAx_CR: a) looping IOMâ-2 time slot data from DU to DD or vice versa (SWAP = ’0’) b) shifting data from TSa to TSb and TSc to TSd in both transmission directions (SWAP = ’1’) c) switching data from TSa to TSb and looping from DU to DD or switching TSc to TSd and looping from DD to DU . TSa is programmed in TSDP10, TSb in TSDP11, TSc in TSDP20 and TSd in TSDP21. Data Sheet 31 2001-11-09 PEF 82902 Functional Description • a) Looping Data TSa TSb TSc TSd CDA10 CDA11 CDA20 CDA21 TSc ’1’ TSd ’1’ DU DD .TSS: TSa TSb .DPS ’0’ ’0’ .SWAP ’0’ ’0’ b) Shifting Data TSa TSb TSc TSd CDA10 CDA11 CDA20 CDA21 TSc ’0’ TSd ’1’ DU DD .TSS: TSa TSb .DPS ’0’ ’1’ .SWAP ’1’ c) Switching Data TSa TSb CDA10 ’1’ CDA11 TSc TSd CDA20 CDA21 DU DD .TSS: TSa .DPS ’0’ .SWAP Figure 13 TSb ’0’ TSc ’1’ TSd ’1’ ’1’ ’1’ Examples for Data Access via CDAxy Registers a) Looping Data b) Shifting (Switching) Data c) Switching and Looping Data Data Sheet 32 2001-11-09 PEF 82902 Functional Description Figure 14 shows the timing of looping TSa from DU to DD via CDAxy register. TSa is read in the CDAxy register from DU and is written one frame later on DD. Figure 15 shows the timing of shifting data from TSa to TSb on DU(DD). In Figure 15a) shifting is done in one frame because TSa and TSb didn’t succeed directly one another (a = 0...9 and b ≥ a+2). In Figure 15b) shifting is done from one frame to the following frame. This is the case when the time slots succeed one other (b = a+1) or b is smaller than a (b < a). At looping and shifting the data can be accessed by the controller between the synchronous transfer interrupt (STI) and the status overflow interrupt (STOV). STI and STOV are explained in the section ’Synchronous Transfer’. If there is no controller intervention the looping and shifting is done autonomously. •. FSC DU TSa TSa µC DD *) TSa STOV ACK WR RD STI CDAxy TSa *) if access by the µC is required Figure 14 Data Sheet Data Access when Looping TSa from DU to DD 33 2001-11-09 PEF 82902 Functional Description • a) Shifting TSa → TSb within one frame (a,b: 0...11 and b ≥ a+2) FSC DU (DD) TSa TSa TSb µC *) STI STOV ACK WR RD STI CDAxy b) Shifting TSa → TSb in the next frame (a,b: 0...11 and (b = a+1 or b